欢迎访问铁路通信信号工程技术,今天是 English

铁路通信信号工程技术 ›› 2023, Vol. 20 ›› Issue (9): 7-10.DOI: 10.3969/j.issn.1673-4440.2023.09.002

• • 上一篇    下一篇

基于UVM的应答器传输模块验证方法研究

刘光宇1,2,马 盼1,2,刘肖婷1,2,孟博洋1,2,林子明1,2   

  1. 1.北京全路通信信号研究设计院集团有限公司,北京 100070;
    2.北京市高速铁路运行控制系统工程技术研究中心,北京 100070
  • 收稿日期:2022-10-20 修回日期:2023-08-31 出版日期:2023-09-22 发布日期:2023-09-25
  • 作者简介:刘光宇(1986—),男,工程师,硕士,主要研究方向:数字集成电路设计与验证,邮箱:liuguangyu@crscd.com.cn。

Research on Verification Method of Balise Transmission Module Based on UVM

Liu Guangyu1, 2,  Ma Pan1, 2,  Liu Xiaoting1, 2,  Meng Boyang1, 2,  Lin Ziming1, 2   

  1. 1. CRSC Research & Design Institute Group Co., Ltd., Beijing 100070, China;
    2. Beijing Engineering Technology Research Center of Operation Control Systems for High Speed Railways, Beijing 100070, China
  • Received:2022-10-20 Revised:2023-08-31 Online:2023-09-22 Published:2023-09-25

摘要: FPGA设计逻辑的不断提升,对其测试的难度也在不断加大,传统的基于开发工具验证的模式已经不能实现其测试需求。针对应答器传输模块(BTM)解码板的FPGA,设计一种基于UVM的验证平台,实现对代码的自动化仿真测试。该平台使用随机驱动加定向测试的方法生成测试激励序列,可通过较少的测试用例实现对FPGA代码的测试覆盖率要求。同时,该平台可在服务器资源允许的情况下,实现对任意数量案例的并行仿真,进一步缩减测试的时间成本。

关键词: 测试平台, 随机测试, 定向用例

Abstract: With the continuous improvement of FPGA design logic, the difficulty of testing is also increasing, and the traditional verification model based on development tool can no longer meet its testing requirements. Aiming at the FPGA of the balise transmission module (BTM) decoding board, this paper designs a verification platform based on UVM, and realizes the automatic simulation test of the code. The platform uses the method of random driver and direct testing to generate test incentive sequences, which can achieve the requirement of test coverage of FPGA code through fewer test cases. At the same time, the platform can realize parallel simulation of any number of cases as the server resources permit, and further reduce the time cost of testing.

Key words: test platform, random testing, direct testcase

中图分类号: